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general description the MAX14912/max14913 have eight 640ma smart high- side switches that can also be configured as push-pull drivers for high-speed switching. the propagation delay from input to switching of the high-side/low-side drivers is 1s (max). each high-side driver has a low on-resistance of 230m (max) at 500ma load current at t a = 125c. the device is configured and controlled either through pins or the spi interface. the spi interface is daisy-chainable, which allows efficient cascading of multiple devices. spi also supports command mode, for the highest detailed diagnostic information. the MAX14912 allows configuration through spi in parallel and serial setting modes, while the max14913 only supports configuration through spi in serial setting mode. open-load detection in high-side mode detects both open-wire conditions in the switch on/off states, and led drivers provide indication of per-channel fault and status conditions. internal active clamps accelerate the shutdown of inductive loads fast in high-side mode. the MAX14912/max14913 are available in a 56-pin qfn 8mm x 8mm package. applications industrial digital outputs plc systems building automation benefts and features low power and heat dissipation ? 230m (max) high-side r on at t a = 125c ? high-effciency 5v/100ma buck regulator fast switching ideal for high-speed control systems ? 0.1s (typ.) propagation delay (high-side mode) ? 0.5s (typ.) propagation delay (push-pull mode) ? 200khz switching-rate capability in push-pull mode ? fast inductive load demagnetization robust operation ? 60v abs max v dd rating ? safe-demagnetization: turn-off of unlimited inductance ? iec61000-4-2 8kv air gap/6kv contact esd protection ? 1kv/42 surge protection with tvs on vdd ? robust spi interface with watchdog and crc ? -40c to +125c ambient operating temperature range extensive diagnostics reduces system downtime ? per driver and chip thermal shutdown ? open-wire detection in high-side mode ? low supply voltage warning ? undervoltage detection ? overvoltage detection on out ? overcurrent detection ? led drivers for visual fault and output state indication flexible interface for ease of design ? serial and/or parallel control interface ? per-channel confguration and monitoring ? wide logic voltage range (1.6v to 5.5v) small package and high integration enables compact high-density i/o modules ? 56-pin qfn 8mm x 8mm package ? eight high-side switches/push-pull drivers ? daisy-chainable spi interface ordering information appears at end of data sheet. 19-7777; rev 3; 8/16 MAX14912/max14913 octal high-speed, high-side switch/push-pull driver
m ax 1491 2 / m ax 1491 3 m ax 1491 2 / m ax 1491 3 o u t 1 v d d fl tr 2 4 v s d i g n d p g n d 2 4 v o u t 1 3 . 3 v v d d c s c l k s d o c l k s d o s d i fa u l t c o ntr o ll e r c m n d / i n 2 g n d v d d g n d spi g p i o v l s r i a l p u s h p l p g n d p u s h p l 1 u f o u t 2 o u t 2 o u t 3 o u t 3 o u t 5 o u t 5 o u t 8 o u t 8 o u t 7 o u t 7 o u t 6 o u t 5 o u t 4 o u t 4 c fp o u t 9 o u t 1 o u t 1 0 o u t 2 o u t 1 1 o u t 3 o u t 1 3 o u t 1 6 o u t 8 o u t 1 5 o u t 7 o u t 1 4 o u t 1 2 o u t 4 o u t 5 o u t 6 l x v 5 3 8 v 1 0 f 100 h v l c fn c fp c fn s r i a l fl tr v 5 l x b u ken vpm p vpm p 1 f , 5 v b u ken fa u l t e n c s e n 200 n f , 5 0 v 200 n f , 5 0 v 100 n f 100 n f 1 f , 5 v c m n d / i n 2 di g ital i so lat o r m ax 1 4 93 5 v dd b v dd a g nd a g nd b di g ital i so lat o r m ax 1 293 1 v d d b v d d a g n d a g n d b 3 . 3 v 1 f 3 8 v o u t i n o u tb 1 o u tb 2 o u tb 3 i n b maxim integrated 2 typical application circuit MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
(all voltages relative to gnd.) v dd ........................................................................ -0.3v to +60v pgnd ................................................................... -0.3v to +0.3v buken, lx ............................................... -0.3v to (v dd + 0.3v) v pmp ................................................ (v dd - 0.3v) to (v dd + 6v) out_ (continuous voltage) ............ (v dd - 49v) to (v dd + 0.3v) v 5 , v l ...................................................................... -0.3v to +6v cfp ............................................ (v dd - 0.3v) to (v pmp + 0.3v) cfn ........................................................ -0.3v to (v pmp + 0.3v) sdo ............................................................. -0.3v to (v l + 0.3v) sdi, clk, cs .......................................................... -0.3v to +6v in_, pushpl, fltr, srial, en, fault , cerr /in4, wdflt/in6 .......................... -0.3v to +6v led_, ld_ ................................................... -0.3v to (v 5 + 0.3v) inductive kickback energy out_ pins: i l < 0.6a ........ unlimited out_ load current .......................................... internally limited continuous-current (any other terminal) ........................ 100ma continuous power dissipation (t a = +70c) qfn (derate 47.6mw/c above 70c) ...................... 3800mw junction temperature ....................................... internally limited storage temperature range ............................ -65c to +150c lead temperature (soldering, 10sec) ............................. +300c thermal resistances qfn56-ep package junction-to-ambient thermal resistance ( ja ), multilayer board ........................................................... 21c/w junction-to-case thermal resistance ( jc ), multilayer board .......................................................... 1.0c/w (note 1) (v dd = +10v to +36v, v 5 = +4.5v to +5.5v, v l = +1.6v to +5.5v, t a = -40c to +125c, unless otherwise noted. typical values are at t a = +25c and v dd = +24v, cdcdc = 10f, ldcdc = 100h, cfly = 200nf, cpump = 10f, unless otherwise noted.) dc electrical characteristics parameter symbol conditions min typ max units supply v dd supply voltage v dd 10.5 36 v v dd supply current i dd hs mode, en = high, out_ outputs high (no switching), no load, v 5 and v l supplied externally 1.1 1.5 ma pp mode, en = high, 100khz switching on all out_, v 5 and v l supplied externally, no load 14 22 v dd undervoltage-lockout threshold v dd_uv v 5 = 5v, v dd rising 8.5 9.5 v v dd undervoltage-lockout hysteresis v dd_uvhyst v 5 = 5v 1 v v dd low-voltage warning threshold v dd_lv v dd falling 12 13 14 v v dd low-voltage warning hysteresis v dd_lvhyst v 5 = 5v 2 v maxim integrated 3 note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
(v dd = +10v to +36v, v 5 = +4.5v to +5.5v, v l = +1.6v to +5.5v, t a = -40c to +125c, unless otherwise noted. typical values are at t a = +25c and v dd = +24v, cdcdc = 10f, ldcdc = 100h, cfly = 200nf, cpump = 10f, unless otherwise noted.) parameter symbol conditions min typ max units v 5 /v l supplies v 5 supply voltage (supplied externally) v 5 4.5 5.5 v v 5 supply current (v 5 supplied externally) i v5 hs mode, en = high, out_ outputs high, no load, no leds connected 2.2 3.2 ma pp mode, en = high, out_ switching at 100khz, no load, no leds connected 8.5 11 ma v 5 undervoltage-lockout threshold v v5_uv v dd = 24v, v 5 rising 3.8 4.2 v v 5 undervoltage-lockout hysteresis v v5_uvhyst v dd = 24v 0.3 v v l supply voltage v l 1.6 5.5 v v l supply current i vl all logic inputs high or low 24 35 a v l undervoltage-lockout threshold v l_uv v l falling 1.12 1.27 1.52 v 5v dc-dc regulator undervoltage-lockout threshold of the dc-dc regulator v dcdc_uvlo v dd rising 6.6 v undervoltage-lockout threshold of the dc-dc regulator hysteresis v dcdc_ uvlohy 0.5 output regulated voltage v dcdc 0ma to 90ma external load current 4.85 5.0 5.15 v current limit i cl_dcdc 100 ma turn-on time t on_dcdc delay from v dd crossing the uvlo threshold until the dc-dc regulator fnishes soft-start 3.0 3.4 3.7 ms switching frequency f dcdc 540 600 660 khz driver outputs (out_) hs mode on-resistance r out_hs hs mode, hs = on, iout_ = -500ma (note 6) 110 230 m hs mode current limit i lim en = high, hs = on, v out__ = v dd -1v 0.64 0.87 1.2 a hs mode current-limit v/i slope (see overcurrent and short-circuit protection section) 150 hs mode weak pulldown current i lkg high-side mode, ol detect = off, hs = off, 7v < v out_ < v dd 65 100 135 a maxim integrated 4 electrical characteristics (continued) MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
(v dd = +10v to +36v, v 5 = +4.5v to +5.5v, v l = +1.6v to +5.5v, t a = -40c to +125c, unless otherwise noted. typical values are at t a = +25c and v dd = +24v, cdcdc = 10f, ldcdc = 100h, cfly = 200nf, cpump = 10f, unless otherwise noted.) parameter symbol conditions min typ max units push-pull mode hs on- resistance r out_pp pp mode, hs = on, en = high, i out_ = -500ma (note 6) 110 230 m push-pull mode ls on- resistance v ol_pp pp mode, ls = on, en = high, i out = 500ma 1 2.5 push-pull mode current limit i lim_pp pp mode, en = high, out_ = high, v out_ = v dd - 1v 0.64 0.87 1.2 a pp mode, en = high, out_ = low, 3v < v out_ < v dd 0.44 0.68 0.81 a open-load detect (out_) open-load pullup current, high-side o ff i ol_hsoff ol detect = on, high-side mode, hs = off, 7v < v out_ < v dd -1v 50 74 100 a open-load detect threshold, high-side off v ol_t ol detect = on, high-side mode, hs = off, led turns off/on 6.4 6.7 7.35 v open-load detect threshold current, high-side on i ol_hson ol detect = on, high-side mode, hs = on, 0v < v out_ < (v dd -1v) 1 2 3 ma debounce filter t deb_ol reliable open-load detection reading is obtained only if both the switch input state and the load level do not change for t deb_ol , high-side = on/off 100 ms logic (i/o) input voltage high v ih v l < 2.5v 0.8 x v l v v l 2.5v 0.7 x v l input voltage low v il v l < 2.5v 0.16 x v l v v l 2.5v 0.3 x v l input threshold hysteresis v ihyst 0.1 x v l v input pulldown resistor r i all logic input pins, except cs (note 2) 140 200 275 k input pullup resistor r i cs input (note 2) 140 200 275 k output logic-high (sdo) v oh i l = -5ma v l - 0.33v v output logic-low v ol i l = +5ma 0.33 v sdo pulldown resistor r l_sdo cs = high 140 200 275 k open-drain outputs ( fault, cerr /in4, wdflt/in6) output logic-low v odl i l = +5ma 0.58 v leakage i odl open-drain output off, pins are at 5.5v -1 +1 a maxim integrated 5 electrical characteristics (continued) MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
(v dd = +10v to +36v, v 5 = +4.5v to +5.5v, v l = +1.6v to +5.5v, t a = -40c to +125c, unless otherwise noted. typical values are at t a = +25c and v dd = +24v, cdcdc = 10f, ldcdc = 100h, cfly = 200nf, cpump = 10f, unless otherwise noted.) parameter symbol conditions min typ max units led drivers (ledh_, ldl_) output voltage high v oh_led ledh = on, i led = 5ma v 5 - 0.3 v output leakage current high i lh ledh_ = off, v = 0v -50 a output voltage low v ol_led ldl = on, i led = 5ma 0.3 v output leakage current low i ll ldl = off, v = 5v 50 a led driver scan rate fled update rate for each led 1.07 1.18 1.31 khz fault-led minimum on-time t fault_on fault led is turned on for at least t fault_on 200 ms protection out_ clamp negative voltage v cl relative to v dd . en = high 49 56 64.5 v channel thermal-shutdown temperature t jshdn junction temperature rising. per channel 167 c channel thermal-shutdown hysteresis t jshdn_hyst 17 c chip thermal shutdown t cshdn temperature rising 150 c chip thermal-shutdown hysteresis t cshdn_hyst 8 c maxim integrated 6 electrical characteristics (continued) MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
(v dd = +10v to +36v, v 5 = +4.5v to +5.5v, v l = +1.6v to +5.5v, t a = -40c to +125c, unless otherwise noted. typical values are at t a = +25c and v dd = +24v, cdcdc = 10f, ldcdc = 100h, cfly = 200nf, cpump = 10f, unless otherwise noted. parameter symbol conditions min typ max units out_ outputs power-up delay t powerup en = high time from v dd > v dd_uv to switches turned-on, v hvbucken = 0v or v dd 5.5 ms enable delay t enable all power supplies above uvlo thresholds; time from en positive edge to switches turned on 0.1 s push-pull switchover delay t d_ppmode delay from high-side to push-pull switchover 45 s output propagation delay lh t pd_lh high-side mode, delay from in_ or positive cs edge to out_ to 0.8 x v dd . c l = 100pf, fltr = low. 0.35 0.7 s push-pull mode, delay from in_ or cs positive edge to out_ rising to 0.8 x v dd . c l = 100pf, fltr = low (figure 2) 0.40 0.7 output propagation delay hl t pd_hl high-side mode, delay from in_ negative edge or cs switching high to out_ falling by 0.5v. r l = 48, fltr = low (figure 1, note 5) 0.1 s push-pull mode, delay between in_ switching low or cs switching high to out_ falling to 0.2 x v dd . c l = 100pf, fltr = low (figure 2) 0.35 0.7 output-to-output propagation skew lh t pd_sk_lh push-pull modes, c l = 1nf, fltr = x (note 3, note 7) -100 0 100 ns output-to-output propagation skew hl t pd_sk_hl push-pull modes, r l = 5k, c l = 1nf, fltr = x (note 7) -100 0 100 ns output rise time t r push-pull mode, 20% to 80% v dd , c l = 100pf, fltr = x (note 7) 0.3 s high-side mode, 20% to 80% v dd , fltr = x (note 7) 0.3 s output fall time t f push-pull mode, 80% to 20% v dd , v dd < 30v, c l = 100pf, fltr = x (note 7) 0.05 maxim integrated 7 ac electrical characteristics MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
(v dd = +10v to +36v, v 5 = +4.5v to +5.5v, v l = +1.6v to +5.5v, t a = -40c to +125c, unless otherwise noted. typical values are at t a = +25c and v dd = +24v, cdcdc = 10f, ldcdc = 100h, cfly = 200nf, cpump = 10f, unless otherwise noted. parameter symbol conditions min typ max units crc error detection (cerr/in4) propagation delay t pdl_cerr srial = high, crc/in3 = high, out_ detects a crc error on sdi data, i source = 5ma 14.5 ns t pdh_cerr srial = high, crc/in3 = high, out_ clears/cerr/in4, i source = 5ma 17 ns watchdog timer watchdog timeout accuracy t wd_acc srial = high, wden/in5 = high. see table 5 for watchdog timeout selection. -10 +10 % glitch filters pulse length of rejected glitch t fpl_gf fltr = high, on en, cs, _in_ pins 80 ns fltr = x, srial and pushpl pins 170 passes pulse length t fd_gf fltr = high, on en, cs, _in_ pins 260 ns fltr = x, srial and pushpl pins 550 glitch filter delay time t d_gf fltr = high, on en, cs, _in_ pins 140 ns fltr = x, srial and pushpl pins 320 spi timing characteristics 2.5v v l < 5.5v clk clock period t ch+cl 50 ns clk pulse-width high t ch 10 ns clk pulse-width low t cl 10 ns cs fall-to-clk rise time t css fltr = low (note 5) 12 ns fltr = high 260 sdi hold time t dh 5 ns sdi setup time t ds 5 ns output data propagation delay t do c l = 10pf. clk falling-edge to sdo stable 30 ns sdo rise-and-fall times t ft 1 ns cs hold time t csh 40 ns cs pulse width high t cspw fltr = low (note 5). 15 ns fltr = high 260 maxim integrated 8 ac electrical characteristics (continued) MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
note 2: all units are production tested at t a = +25c. specifications over temperature are guaranteed by design. note 3: channel-to-channel skew is defined as the difference in propagation delays between channels on the same device with the same polarity. note 4: all logic input pins except cs have a pulldown resistor. cs has a pullup resistor. note 5: specification is guaranteed by design; not production tested. note 6: excludes bond wire resistance. note 7: x - means do not care. note 8: bypass each v dd pin to agnd with a 1f capacitor as close as possible to the device for high-esd protection. (v dd = +10v to +36v, v 5 = +4.5v to +5.5v, v l = +1.6v to +5.5v, t a = -40c to +125c, unless otherwise noted. typical values are at t a = +25c and v dd = +24v, cdcdc = 10f, ldcdc = 100h, cfly = 200nf, cpump = 10f, unless otherwise noted. parameter symbol conditions min typ max units esd v esd out_ pins. contact (note 8) 8 kv out_ pins. air discharge 15 kv all other pins. human body model 2 kv parameter symbol conditions min typ max units 1.6v v l < 2.5v clk clock period t ch+cl 60 ns clk pulse-width high t ch 13 ns clk pulse-width low t cl 13 ns cs fall to clk rise time t css fltr = low (note 5) 15 ns fltr = high 260 sdi hold time t dh 10 ns sdi setup time t ds 10 ns output data propagation delay t do c l = 10pf. clk falling-edge to sdo stable 40 ns sdo rise-and-fall times t ft 2.5 ns cs hold time t csh 40 ns cs pulse-width high t cspw fltr = low (note 5) 20 ns maxim integrated 9 esd characteristics ac electrical characteristics (continued) MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
figure 1. high-side mode timing characteristics v l gnd gnd in_ 50% 0.5v 0.5v t pdhs_lh t pdhs_lh t pdhs_hl t pdhs_hl 50% 50% 50% 80% 20% 80% 20% t r t f t r t f v dd - 0.5v v dd - 0.5v v dd v dd gnd gnd v l cs o_ o_ o_ o_ v dd v dd gnd gnd 0.1f v l v l gnd in_ / cs pushpl fltr o_ v 5 pgnd 1f v dd v dd 1f v5 c l r l 50? test source MAX14912/ max14913 test circuits/timing diagrams maxim integrated 10 MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
figure 2. push-pull mode timing characteristics 0.1f v l v l gnd pushpl fltr pgnd 1f v dd v dd 50 test source MAX14912/ max14913 v l gnd in_ o_ o_ t pdpp_lh t pdpp_lh t pdsk_lh t pdsk_hl t pdpp_hl t pdpp_hl 50% 50% 50% 50% t r t f t r t f 0.2 x v dd 0.2 x v dd 0.8 x v dd 0.8 x v dd 0.8 x v dd 0.2 x v dd 80% 20% v dd v dd gnd gnd v l gnd cs o_ o_ v dd v dd gnd gnd o_ v 5 1f v 5 c l r l in_ / cs test circuits/timing diagrams (continued) figure 3. spi timing diagram cs clk sdi sdo t css t cl t ds t ft t dh t ch t do t csh maxim integrated 11 MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
(v dd = 24v; v 5 = 5v, v l = 3.3v, t a = +25c, unless otherwise noted.) 0 . 0 0 0 . 0 5 0 . 1 0 0 . 1 5 0 . 2 0 0 . 2 5 0 . 3 0 - 4 0 1 0 6 0 1 1 0 h igh- s i d e p r o p a g a tion d el a y ( s) te m pe r a t ur e ( oc ) h ig h - s i d e p r o p a g a t io n d e l a y vs . t empe ra t ur e t oc 03 v d d = 10v to 36v , o u tp u t l o a d 4 8 ? || 100p f h igh - to - l o w h igh- s i d e m o d e l o w - to - h igh 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 100 120 140 160 180 200 220 240 0 200 400 600 low - side r on ( ? ) high - side r on ( m ? ) i load ( ma ) r on resistance vs. load current toc01 high - side r on v dd = 10v, 24v, & 36v 10v 36v 24v low - side r on v dd = 10v, 24v, or 36v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 10 20 30 40 i dd ( ma ) v dd (v) supply current vs. supply voltage toc05 no loads, no switching outputs high, dc - dc active high - side mode push - pull mode 0 0.5 1 1.5 2 2.5 0 50 100 150 200 250 -40 10 60 110 low - side r on ( ? ) high - side r on ( m ? ) temperature ( o c ) r on resistance vs. temperature toc02 high - side low - side 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 0 50 100 150 200 i dd (ma) frequency (khz ) supply current vs. switching frequency toc06 duty cycle 50% v dd = 10v v dd = 24v push - pull mode, dc - dc active v dd = 36v all channels switching, no loads 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -40 10 60 110 propagation delay ( s ) temperature ( c ) propagation delay vs. temperature toc04 push - pull mode high - to - low v dd = 24v, output load 1k ? || 100pf low - to - high 0.00 1.00 2.00 3.00 4.00 5.00 6.00 0 10 20 30 40 50 led driver output (v) i load (ma) led driver output vs. load current toc07 low - side high - side maxim integrated 12 typical operating haracteristics MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
pin name function led drivers 1, 2 ldls5-8, ldls1-4 status led cathode outputs (open-drain low-side) 3, 4 ldlf5-8, ldlf1-4 fault led cathode outputs (open-drain low-side) 38C41 ledh15, ledh26, ledh37, ledh48 led anode connections (open-drain high-side). connect a resistor in series to set the diode current. power supply 5 cfn charge-pump flying capacitor 6 cfp charge-pump flying capacitor. connect a 200nf/50v capacitor to cfn. 7 vpmp charge-pump output. connect a 10f/5v capacitor between vpmp and v dd . vpmp is not intended for use as a power supply for other devices. 8, 21, 36, 50 gnd (4x) ground. connect all gnd pins together. 9 lx dc-dc converter switching output. connect lx to the switching-side of the inductor . top view qfn 8 mm x 8 mm 15 17 16 18 19 20 21 22 23 24 25 26 27 28 cs + srial v dd out 1 v dd out 2 gnd v dd out 3 v dd out 4 v dd ol / in 1 cmnd / in 2 uvlo en v dd out 8 v dd out 7 gnd v dd out 6 v dd out 5 v dd buken pushpl 48 47 46 45 44 43 54 53 56 55 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 40 39 38 37 36 35 34 33 32 31 30 29 sdo sdi clk v l pgnd lx gnd vpmp cfp cfn ldlf 1 - 4 ldlf 5 - 8 ldls 1 - 4 ldls 5 - 8 wden / in 5 cerr / in 4 crc / in 3 wdflt / in 6 cnfg / in 7 s 16 / in 8 fltr gnd v 5 ledh 15 ledh 26 ledh 37 ledh 48 fault ma max14913 x 14912/ maxim integrated 13 pin confguration pin description MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
pin name function 10 pgnd ground for the dc-dc converter. connect to gnd. 11 v l logic supply input. v l defnes the levels on all i/o logic interface pins. bypass v l to gnd through a 100nf ceramic capacitor. 17, 19, 22, 24, 26, 45, 47, 49, 52, 54 v dd (10x) supply voltage, nominally 24v. connect all v dd together. bypass v dd to gnd through a 1f capacitor. 37 v 5 5v supply input. v 5 can be powered by an external 5v supply or the internal 5v buck. bypass v 5 to gnd through a 10f ceramic capacitor. 44 buken enable input for buck regulator. buken should be permanently connected to either v dd or gnddo not switch buken. connect buken to gnd if not using the internal buck. connect buken to v dd to use the internal buck. 56 uvlo uvlo is an open-drain, undervoltage indicator of the v dd supply. serial interface 12 sdo serial-data output. spi miso data output to controller. 13 sdi serial-data input. spi mosi data from controller. 14 clk serial-clock input from spi controller 15 cs chip-select input from controller logic interface 16 srial serial/parallel select input. drive srial high to set the MAX14912/max14913 outputs through the serial interface. drive srial low to set the MAX14912/max14913outputs through the parallel (_/in) pins. srial does not affect serial readback of diagnostic/status information. 27 ol/in1 open-load select input/in1 input. in serial mode (srial = high), drive ol/in1 = high to enable open-load detection on all eight out_ outputs when in high-side operation. in parallel mode (srial = low), ol/in1 sets out1 on/off/high/low. 28 cmnd/in2 command mode spi input/in2 logic input. in serial mode (srial = high), cmnd/in2 enables command-based spi access (see detailed description section for details). in parallel mode (srial = low), cmnd/in2 sets out2 on/off/high/low. 29 crc/in3 crc select input/in3 input. in serial mode (srial = high), drive crc/in3 = high to enable crc error detection on serial data. in parallel mode (srial = low), crc/in3 sets out3 on/off/high/ low. 30 cerr/in4 crc error detection output/in4 input. in serial mode (srial = high) with error checking enabled (crc/in3 = high), cerr/in4 is an open-drain output whose transistor turns on when the device detects an error on sdi data. in parallel mode (srial = low), cerr/in4 sets out4 on/off/high/low. 31 wden/in5 watchdog enable input/ in5 input. in serial mode (srial= high), wden/in5 enables the watchdog timer. in parallel mode (srial= low), wden/in5 sets out5 on/off/high/low. 32 wdflt/in6 watchdog fault output/in6 input. in serial mode (srial = high), wdflt/in6 is the open-drain watchdog fault output, which turns on when a watchdog fault is detected while wden/in5 is high. in parallel mode (srial = low), wdflt/in6 sets out6 on/off/high/low. maxim integrated 14 pin description (continued) MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
pin name function 33 cnfg/in7 confgure input/in7 input. in serial mode (srial = high), drive cnfg/in7 high to enable per- channel confguration through the serial interface. in serial mode, drive cnfg/in7 low to allow setting the out_ outputs through the serial interface. in parallel mode (srial = low), cnfg/in7 sets out7 on/off/high/low. 34 s16/in8 16-bit serial select/in8 input. in serial mode (srial = high), drive s16/in8 high to select 16-bit serial-interface operation. drive s16/in8 low in serial mode for 8-bit serial operation. in parallel mode (srial = low), s16/in8 sets out8 on/off/high/low. 35 fltr glitch filter enable input. set fltr high to enable glitch fltering on all parallel logic inputs and cs. 42 fault open-drain fault output. the fault transistor turns on low when a fault condition (driver shutdown or open-load detect) occurs. 43 pushpl push-pull, high slew-rate confguration input. when pushpl is set high, all out_ pins operate in push-pull mode. when pushpl is set low, all out_ pins operate in high-side mode. 55 en output enable input. driving en low turns all high-side out_ switches of f, and three-states all push-pull out_ drivers and turns all led drivers off. driving en high enables normal operation. switch/driver outputs 18, 20, 23, 25, 46, 48, 51, 53 out1Cout8 driver output n. may be confgured as a high-side switch or push-pull output. maxim integrated 15 pin description (continued) MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
s 1 6 / i n 8 gn d m a x 149 1 2 m a x 149 1 3 p a r a l l e l i n te r fa c e l e d h 1 5 l e d h 2 6 l e d h 3 7 l e d h 4 8 ol / i n 1 c m n d / i n 2 c r c / i n 3 c e r r b / i n 4 s r i a l w d e n / i n 5 w d fl t / i n 6 c n fg / i n 7 l e d d r i v e r s f a u l t , l e v e l l d l s 1 - 4 l d l s 5 - 8 l d l f 1 - 4 l d l f 5 - 8 e n f a u l t s h u t d n ol s e r i a l i n t e r f a c e s d i c l k c s s d o p u s h p l u v m on i tor v d d c on fi g a n d s e tt i n g v l v 5 v d d e n u v l o w a t c h d og b u c k charge pump c fp c fn v p m p f l tr l x d r i v e + m on i tor e n o u t 7 v d d b u k e n u v l o v d d p gn d d r i v e + m on i tor e n o u t 8 v d d d r i v e + m on i tor o u t 2 v d d d r i v e + m on i tor o u t 1 v d d d i a gn os t i c s v 5 maxim integrated 16 functional (or block) diagram MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
detailed description high-side mode the high-side drivers (hs) have 230m (max) on-resistance when sourcing 500ma at t a = +125c. the out_ output voltage can go below ground, as can occur during inductive load turn-off/demagnetization. internal clamping diodes limit the negative excursion to (v dd - v cl ) and allow free-wheeling currents to demagnetize the inductive loads quickly. low-side transistors (ls) can be switched in to provide push-pull operation. fast discharge of ground-connected rc loads is achieved by push-pull drive. in push-pull mode, the out_ outputs are clamped to gnd. output parallelization the devices support paralleling of channels in high-side mode to provide higher current. the channels can be paired (1-2, 3-4, 5-6, and 7-8) by setting two bits of the spi register 3: joinup and joindw (see table 6 ). when joindw = 1, out1 and out2 are connected together, and out3 and out4 are connected together, and: input signals related to channels 2 and 4 are neglected; output status is determined by inputs 1 and 3; push-pull mode is disabled. when joinup = 1, out5 and out6 are connected together, and out7 and out8 are connected together, and: input signals related to channels 6 and 8 are neglected; output status is determined by inputs 5 and 7; push-pull mode is disabled. the above configuration can be used without any additional external zener clamping. besides pairing of drivers through internal configuration, multiple outs can be operated in parallel by tying the out_ together and driving the inputs simultaneously. in this case, an external zener clamp is required per output set for quenching the energy during inductive load turn- off. the external clamp voltage of this zener diode must be lower than the minimum internal clamp voltage (v cl (min)). the reason is that there is channel-to-channel variation between the internal clamp voltages. without an external zener diode, during turn-off of channels connected in parallel, the internal clamp with the lowest clamp voltage turns on and dissipates all the energy. channel diagnostics for fault detection remains independent in case of paralleling the outputs. open-load/wire detection detection of an open-load condition can be enabled on a per-channel basis through serial configuration, or glob - ally in serial mode through the ol/in1 input. open-load detection works in high-side mode only. it operates with the hs driver either on or off. when the hs switch is off, a current source is enabled, which pulls out_ to v dd when the wire is open. if the out_ voltage is above v ol_t , an open load is signaled. when the hs switch is on, the voltage across the hs switch is monitored. if this drop is below a load current of i ol_hson , an open-load fault is reported. the switch input state and the load condition must both be stable for at least t deb_ol to get a reliable reading. when an open-load condition is detected on an output: 1) the f_ bit is set for that output in the serial diagnostic data. 2) the fault led is turned on for at least 200ms for that channel. 3) the open-drain global fault transistor is turned on for at least 200ms. figure 4. open-wire load detection i ol _ hsoff o ut _ hs ls open wire vdd v ol_ t open gnd r l maxim integrated 17 MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
watchdog the watchdog timer allows monitoring activity on the cs input in serial mode (srial = high). drive wden/in5 high to enable the watchdog function. the watchdog monitors and expects activity on the cs input. the wd timer is reset at every cs falling edge. if the timer is not reset after the timeout delay, see table 8 ), all out_ outputs are turned off and the watchdog fault output (wdfltb/in6) transitions low until the next cs falling edge. the watchdog timeout can be selected in spi command mode (see the configuration and monitoring section). bits selection in register 3: wd[1:0] = 00 for 0.9s, wd[1:0] = 01 for 0.45s and wd[1:0] = 10 for 0.15s. the default value is 0.9s. thermal management every drivers temperature is constantly monitored while v dd > v dd_uv . if the temperature of a driver rises above the thermal-shutdown threshold of t jshdn , that channel is automatically turned off for protection. the drivers are turned on again once the temperature drops by a hysteresis margin of t jshdn_hyst . both high and low-side drivers are thermally protected with a per-driver protection circuit. when a driver turns off due to thermal shutdown: 1) a fault is indicated through the global fault output. 2) the f_ bit of that channel is set in the diagnostic byte in the spi interface. 3) the fault led driver turns on for that channel. the device also has a chip thermal shutdown that triggers a fault output and all the channels shut down if the tem- perature rises above t cshdn . overcurrent and short-circuit protection in the event of a short-circuit or high current at an out_ output, the load current is limited on a per-channel basis to i lim_hs for the high-side (hs) driver and to i lim_pp for the low-side (ls) driver. additionally, when a short circuit is detected, the affected out_ output is put in a safe slow- mode in order to prevent damages in case its in_ input is switching at a high frequency. in order to restore normal operation, the in_ input of the affected channel has to be kept low for at least 20ms. while in slow-mode, the low-to-high and high-to-low transitions at out_ are slew- rate limited to around 3v/s. a short-circuit or overcurrent generally creates a temperature rise in the chip; both the hs and ls fets temperatures are continuously monitored. when any switch temperature exceeds t jshdn , the corresponding out_ output is put in a high-impedance state until the temperature falls by the hysteresis. if the case temperature is below t cshdn , a short circuit on one output will allow the other outputs to operate normally. the hs current-limit circuit features a controlled dv/di slope that improves stability with inductive loads. in other words, the current is limited to a nonconstant value that increases with (v dd - v out ) with a slope of 1a/150v. figure 5. watchdog timer watchdog wden/in5 cs wdflt/in6 maxim integrated 18 MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
undervoltage lockout when the v l , v dd , or v 5 supply voltages are under their respective uvlo thresholds, all out_ outputs are turned off (three-stated) and the open-load detect current sourc - es are turned off; they automatically turn back on once the v dd /v 5 rises to above the uvlo thresholds. undervoltage conditions can be read out through spi. the uvlo open-drain output pin indicates whether v dd is below the v dd_uv threshold. led drivers the 4 x 4 led driver crossbar matrix offers a pin-optimized configuration for driving 16 leds. per-channel output status and the fault conditions are indicated by individual leds. if a fault led is turned on for an output, the corresponding level led is always turned off. this mitigates false information about the status of the affected out_ pin. for every current-limiting resistor (r), each of the four leds in the vertical string are pulsed so that current only flows through one led at any given time. therefore, the resistors (r) determine the led current through one led and should be chosen according to the leds current/light- intensity requirements. every led that is on, is pulsed on with a 25% duty cycle. confguration and monitoring the MAX14912/max14913 can be configured, set, and monitored through either a parallel or serial interface. the serial interface allows greater configuration flexibility and provides more monitoring information. for the max14913, in parallel setting mode (srial = low), the spi cannot be used for configuring the device, spi is only available for monitoring. global confguration pin-based configuration does not require the use of the spi interface. it is global and allows for the configuration of all out_ as high-side outputs, push-pull outputs, and enables open-load detection. see table 1 for details. in cases where configuration is possible through the parallel and/or serial interface, table 2 documents the priority. figure 6. led output status and fault-detection matrix 5 v f a u l t 1 - 4 f a u l t 5 - 8 status 1 - 4 status 5 - 8 ldlf ldlf ldls ldls 1 - 4 5 - 8 1 - 4 5 - 8 le d h 1 5 le d h 2 6 le d h 3 7 le d h 4 8 r r r r m a x 1491 2 m a x 1491 3 g n d maxim integrated 19 MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
table 1. global configuration pins note 1: pushpl and srial are always filtered, independent of fltr logic. table 2. configuration priority input srial configuration pushpl x confgures all out_ outputs as push-pull or high-side. 0 = all drivers in high-side mode unless confgured as push-pull by serial interface. 1 = all drivers in push-pull mode. ol/in1 1 enables global open-load detection in serial mode. 0 = open-load detection disabled unless enabled by serial interface. 1 = open-load detection enabled for all high-side mode switches. crc/in3 1 enables crc generation and error detection on the serial interface. 0 = crc error detection disabled. 1 = crc error detection enabled. fltr x enables anti-glitch fltering on all logic input pins except sdi and clk. (note 1) 0 = glitch fltering disabled. 1 = glitch fltering enabled. wden/in5 1 enables watchdog on the spi interface. 0 = watchdog disabled. 1 = watchdog enabled. configuration srial priority push-pull/ high-side 1 pushpl result low out_ drivers in high-side mode, unless confgured individually as push-pull through the serial interface. high all out_ drivers in push-pull mode, independent of serial confguration. open-load detection 1 ol/in1 result low open-load detection off, unless confgured individually through the serial interface. high open-load detection enabled on all out_ outputs that operate in high-side mode. maxim integrated 20 MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
parallel interface: setting the out_ output driver the parallel mode (srial = low) uses one input pin (in_) to set each output (out_). table 3 shows the settings that depend on the configured mode. in parallel setting mode (srial = low), the max14913 can only be configured via the global configuration inputs: pushpl and fltr, not on a per-channel basis through spi. this means that all high-side drivers are either in high-side or push-pull operation. open-load detection is enabled and cannot be disabled in parallel setting mode. the MAX14912 can be configured with full flexibility in parallel setting mode. serial controller interface the serial interface can be used in all setting modes. it is based on cpol = low and cpha = low, meaning that the sdi data is latched-in on the rising edge of clk and new sdo data is written on the falling edge of clk. the default idle clk state needs to be low. the sdo output is only actively driven when the spi master drives cs low, it is otherwise weakly pulled down by an internal 200k? resistor when cs is high. the spi interface provides per channel and detailed global diagnostics. in serial setting mode (srial = high), the outputs are set on/off/high/low by the serial interface. serial mode also allows per channel and global configuration. in parallel setting mode (srial = low), the max14913 does not allow configuration through spi, while the max1912 can be configured per channel and globally. the spi interface can be operated in either command mode or direct mode. command mode is available in both parallel and serial modes and provides higher information content and supports more configuration options. see table 4 for details. direct mode spi is only available in serial setting mode (srial = high). in direct spi mode, output setting and per channel configuration is written directly (without a command byte) and diagnostics data is provided either in an 8 or 16-bit spi cycle. in both command and direct spi modes, when the high- side/push-pull drivers are set on/off/high/low via spi, the outputs change state at the end of the spi cycle, on the rising cs edge, with a sub 1s propagation delay, as defined in the electrical properties table. in direct and command mode spi, diagnostic and status information is sampled at the beginning of each spi cycle, initiated by the falling cs edge and is then sequentially written out on sdo on each falling clk edge. command spi mode allows reading back the chip configuration and status and diagnostics, as selected via the command byte. this information is then written out on the following spi cycle. table 3. srial = low table 4. spi interface modes selection and description driver mode in_ out_ state high-side 0 high-side off high-side 1 high-side on push-pull 0 push-pull output low push-pull 1 push-pull output high pin result spi mode srial cmnd /in2 cnfg /in7 s16 /in8 bits sdi sdo notes direct spi 8-bit/16-bit operation 1 0 0 0 8 per-channel out_ setting per-channel fault out set by spi. fault is the real-time status of the fault (driver shutdown or open-load) 1 16 per-channel out_ setting and hs/pp selection per-channel fault and level 1 0 1 0 8 per-channel confg: hs/pp per-channel fault out level does not change 1 16 per-channel confg: hs/pp and ol detection on/off per-channel fault and level command mode 1 1 x x 16 8-bit-command + 8-bit data previous command output out level may or may not change depending on command 0 x x x 16 8-bit-command + 8-bit data previous command output out set by inx pins. MAX14912 allows spi confguration. max14913 does not allow spi confguration. maxim integrated 21 MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
daisy-chain spi operation the device supports daisy-chain operation, allowing control/ monitoring of multiple MAX14912/max14913 devices from a single serial interface with one common chip-select signal. the identical data that is clocked into sdi, is clocked out of sdo with a one spi cycle delay. this is illustrated in figure 8. direct spi serial interface: 8-bit mode srial = high, cmnd = low, s16 = low. figure 9 shows an 8-bit cycle that reads the per-channel diagnostic data and sets/configures the outputs in a single 8-bit cycle. table 5 illustrates the meaning of the spi bits. the data returned on sdo is the per-channel fault status. pin cnfg is used to select whether the sdi input bits set the output level or the output mode (high-side or push- pull). figure 7. daisy-chain connection figure 8. spi cycle in 8-bit direct spi mode f i f o - i c 3 d a t a - i c 3 d i a g - i c 3 sdo f i f o - i c 2 d a t a - i c 2 d i a g - i c 2 sdo f i f o - i c 1 d a t a - i c 1 d i a g - i c 1 sdo max max14913 14912/ max max14913 14912/ max max14913 14912/ mcu sdi clk cs clk mosi cs miso sdi cs clk clk cs sdi d 7 d6 d5 d4 d3 d2 d1 d8 f7 f6 f5 f4 f3 f2 f1 f8 cs clk sdi sdo maxim integrated 22 MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
direct spi serial interface: 16-bit mode srial = high, cmnd = low, s16 = high figure 9 shows a 16-bit read/write cycle that reads the per-channel diagnostic data and configures/sets the outputs in a single 16-bit cycle. the data returned on sdo is the per-channel fault status. the cnfg pin is used to select whether the input bits sent to sdi set the output level or the output mode (high-side or push-pull). moreover, in 16-bit mode, the open-load detection can be enabled on a per-channel basis. table 5. 8-bit spi direct mode bit definition table 6. 16-bit spi direct mode bit definition bit bit value cnfg definition d_ 0 low in high-side mode: set hs off in push-pull mode: hs off, ls on 1 low in high-side mode: set hs switch on in push-pull mode: set hs switch on, ls off 0 high confgure high-side mode 1 high confgure push-pull mode f_ 0 x no fault 1 x fault (thermal protection or open load bit bit value cnfg definition d_ 0 low in high-side mode: hs off, ls off in push-pull mode: hs off, ls on 1 low hs on, ls off c_ 0 low high-side mode 1 low push-pull mode d_c_ 00 high high-side mode; open-load detection defned by ol/in1 pin 01 high push-pull mode 10 high high-side mode with open-load detection 11 high not used f_ 0 x no fault 1 x fault status (thermal protection or open- load) l_ 0 x output level < 7v 1 x output level > 7v figure 9. spi cycle in 16-bit direct spi mode cs clk sd o sdi f 7 f 6 f 5 f 4 f 3 f 2 f 1 f 8 l 8 l 7 l 6 l 5 l 4 l 3 l 2 l 1 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 c 8 c 7 c 6 c 5 c 4 c 3 c 2 c 1 maxim integrated 23 MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
command mode spi cmnd = high in serial setting mode (srial = high), command spi mode allows setting, configuration and monitoring. in parallel setting mode (srial = low) command mode allows monitoring. while the MAX14912 supports spi configuration in parallel mode, configuration is not supported in the max14913. in command mode, the input is always a command + data word; pins cnfg, s16, and ol are ignored. the output word returns the information requested during the previous spi cycle. table 7 lists the registers accessible in command mode, while table 8 l ists the commands and their effect. in command mode, a latched version of all faults is available. in other words, the device keeps any fault in memory until the user decides to clear the fault registers. each bit of fault registers 4, 5, and 6 is set as soon as its corresponding real-time fault signal goes high. at the end of any spi cycle during which the sdi msb (the z bit) has been set to 1, all fault registers are cleared at once (see table 8 ). if [srial = high and cmnd = high], the global fault signal is latched as well (see table 9 for more details on the global fault signal). otherwise, it is a real-time global fault status. in command mode, both the latched and the real-time faults can be read out. all commands except #4 returns the same real-time data as in the 16-bit mode. command #4 can be used to read any register and, for fault registers 4, 5, and 6, it returns both the latched and real-time value of any fault signal. table 7. spi registers (accessible only in command mode) reg r/w purpose 7 6 5 4 3 2 1 0 0 r/w switch/driver settings (note 10) in8 in7 in6 in5 in4 in3 in2 in1 default 0 0 0 0 0 0 0 0 1 r/w push-pull/high-side confguration (note 11) pp8 pp7 pp6 pp5 pp4 pp3 pp2 pp1 default 0 0 0 0 0 0 0 0 2 r/w open load detect enable (note 11) ol_en8 ol_en7 ol_en6 ol_en5 ol_en4 ol_en3 ol_en2 ol_en1 default 0 0 0 0 0 0 0 0 3 r/w watchdog confg. and channel paralleling (note 11) joinup joindw wd1 wd0 default 0 0 0 0 0 0 0 0 4 r per-channel open-load condition ol8* ol7* ol6* ol5* ol4* ol3* ol2* ol1* 5 r per-channel thermal shutdown thsd8* thsd7* thsd6* thsd5* thsd4* thsd3* thsd2* thsd1* 6 r global faults wdfault crcfault dcdc current- limit 8ckmult error* thsdglob* 5v uvlo v dd uvlo v dd warn 7 r out overvoltage detection (note 9) ov8 ov7 ov6 ov5 ov4 ov3 ov2 ov1 note 9: bits are set when the out_ voltage is higher than v dd . these bits are real-time. note 10: register 0 can be written to, but will not change the output states in parallel (srial = low) setting mode, since the outputs are then only set through the in_ pins. note 11: registers 1, 2, 3 can be written to in the max14913, but will n ot change the confguration in parallel (srial = low) setting mode. * faults are stretched in time to a minimum duration of 200ms. maxim integrated 24 MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
table 8. command mode protocol command no. function sdi sdo valid on next cycle comment command data 0 set out state (reg 0) (note 15) z0000000 dddddddd ffffffff.llllllll d = 0 : hs off; ls on (in pp) d = 1 : hs on; ls off l: output level f: fault (real-time) 12 z = 1: clear fault registers 13 1 set hs/pp mode (reg 1) (note 16) z0000001 dddddddd ffffffff.llllllll d = 0 : hs mode d = 1 : pp mode 2 set ol detection (reg 2) (note 16) z0000010 dddddddd ffffffff.llllllll d = 0 : ol detection off d = 1 : ol detection on (hs mode) 3 set confguration (reg 3) (note 16) z0000011 0000jjab ffffffff.llllllll ab: watchdog 00 = 0.90s 01 = 0.45s 10 = 0.15s j = 1: channels are coupled (pp disabled) 4 read register (note 14) z0100000 00000nnn aaaaaaaa.qqqqqqqq nnn = 0,1,2,3: q = reg value, a = 0 nnn = 4,5,6: q = reg value, a = real_time nnn = 7: q = 0, a = real_time 5 read real-time status (note 12) z0110000 ffffffff.llllllll f-l status readout (real-time). no data is written note 12: f bits are the logical or of thermal protection and open-load detection real-time signals. note 13: any fault bit inside registers 4, 5, and 6 are set as soon as its corresponding event happens. all fault registers are cleared only by setting z = 1 (this is possible during any command cycle). the registers get cleared at cs rising edge. if z = 1 the registers are not cleared in case of spi communication error (crc, 8-ck). if srial = 1 and cmnd = 1, the z bit clears also the fault irq signal. note 14: the q bits are the value of the fault registers (that need to be cleared by means of the z bit). the a bits are the corresponding real-time values (i.e., the real-time fault signals). the real-time values are stretched by 200ms. therefore, they have a time resolution of ~200ms. note 15: in parallel setting mode (srial = low), writing to this registers does not change the real-time values or settings. these can only be changed through pins. note 16: for the max14913 only, in parallel setting mode (srial = low), writing to these registers does not change the configuration. maxim integrated 25 MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
table 9. fault summary fault name what it checks effect on fault pin reg bit(s) name behavior per-channel thermal shutdown (note 17) temp (hs) > 170c or temp (ls) > 170c single-channel hs and ls are turned off immediately. fault (note 18) pin goes low on any fault; if command-mode: pin goes high when z bit is set, else: pin goes high when no faults reg 5 global thermal shutdown die-center temperature > 150c all channels hs and ls are turned off. fault reg 6 bit 3 channel open-load detection (if enabled) hs mode only. hs on: current < 2ma hs off: current < 80a fault reg 4 v dd undervoltage- lockout v dd < v dd_uv all channels hs and ls are turned off; all leds off uvlo goes low reg 6 bit 1 v 5 undervoltage- lockout v 5 < v v5_uv all channels hs and ls are turned off; all leds off reg 6 bit 2 v dd warning v dd < v vdd_warn reg 6 bit 0 watch-dog (if enabled) activity on cs: fault if no falling-edge for more than 1.2s (or 600ms or 200ms) wdflt goes high; goes low at next cs falling-edge reg 6 bit 7 no 8-multiple ck pulses number of ck pulses during a cs low period not a multiple of 8 spi input data is discarded fault goes low on cs rise; reg 6 bit 4 crc error detection (if enabled) received data does not match the fcs word spi input data is discarded cerr goes high; goes high on next cs rise if fault does not happen again reg 6 bit 6 note 17: the hs or ls fets are turned on/off according to the thermal protection signal generated by the analog circuit. on the other hand, inside the logic circuit the thermal-protection signal is maintained high for at least 200ms (to flter out the ~10ms hysteretic cycling of the fet temperature). note 18: in command mode the fault pin behaves as an irq latched signal and can be cleared only by setting the z bit to 1 (as for any other fault register). in all other modes, fault is the logical or of the real-time faults. maxim integrated 26 MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
error detection on the serial interface crc detection in serial mode (srial = high), error-detection of the serial data can be enabled to minimize incorrect operation/ misinformation due to data corruption of the sdi/sdo sig - nals. if enabled, the devices performs error detection on sdi data received from the controller, calculates a crc on the sdo data sent to the controller, and appends a check byte to the sdo diagnostics/status data it sends to the controller. this ensures that the data it receives from the controller (setting/configuration), as well as the data that it sends to the controller (diagnostics/status), has a low likelihood of undetected errors. setting the crc/in3 input high enables crc error detection. a crc frame-check sequence (fcs) is then sent along with each serial transaction. the 7-bit fcs is based on the generator polynomial (x7 + x5 + x4 + x2 + x + 1). the crc initialization condition is 0x7f. when crc is enabled, the device expects a check byte appended to the 8 or 16-bit sdi program/configuration data it receives. the check byte has the format shown in figure 10. the 7-bit fcs bits (cri_) are calculated on the 8/16-bit data, including the 1 in the first position of the check byte. therefore, the crc is calculated on 9 or 17 bits. cri1 is the lsb of the fcs. the device verifies the received fcs. if no error is detected, it sets the out_ outputs and/or changes con - figuration per the sdi data. if a crc error is detected, the device does not change the out_ outputs and/or does not change its configuration. instead, it sets the cerrb/ in4 output low (i.e., the open-drain cerrb/in4 nmos output transistor is turned on) and sets the cerr (crc error) bit in the check byte that it appends to the 8/16-bit sdo diagnostic/status data returned to the controller dur - ing the following serial communication cycle. in command spi mode, register 6 also reflects an crc error condition. the check byte the device appends to the 8/16-bit diag - nostics/status data has the format shown in figure 11. cerr is the error-feedback bit that it sends back to the controller to signal that a crc error was detected on the previous sdi data reception. note that cerr is one state delayed (i.e., it indicates if an error was detected in the previous spi data reception). the reason for the one- cycle delay is due to the daisy-chain scheme. cro_ are the crc bits that the device calculates on the 8/16-bit diagnostics and/or status data, including the cerr bit (i.e., calculated on 9/17 bits). this allows the controller to check for errors on the sdo data received from the device. clock count for multiples of 8 for each spi cycle (between cs going low to cs going high), the device counts the number of clk pulses. the 8ckmult error flag (see table 7 ) is asserted (goes high) and the fault pin is asserted (goes low) if the counted clk pulses are not a multiple of 8. in this case, the sdi data is ignored. figure 10. sdi check byte expected from controller figure 11. sdo check byte sent by device c c c c c c c c c cs c s c c c c c c c maxim integrated 27 MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
applications information pcb layout and circuit recommendations capacitor between vpmp and v dd : 10f 5v; capacitor between cfn and cfp: 200nf 50v; capacitor on v 5 : only one 10f plus a ceramic 100nf as fast bypass capacitor close to each chip. a 1206 footprint 10f cap is recommended; lx trace must be as short as possible; connection between the inductor and v 5 can be long; inductor is 100h: i sat > 0.35a, dcr ~1 (e.g., the coilcraft lps4018-104ml); gnd and v dd connections: dedicated pcb planes for gnd and another for v dd are recommended. driving capacitive loads when charging/discharging purely capacitive loads with a push-pull driver, the driver dissipates power that is pro - portional to the switching frequency . the power can be estimated by p d ~ c x v dd 2 x f sw , where c is the load capacitance, v dd is the supply voltage, and f sw is the switching frequency. for example, in an application with a 1nf load and 100khz switching frequency, each driver dissipates 130mw at v dd = 36v. when driving purely capacitive loads, consider a maximum capacitance of approximately 10nf. driving inductive loads during turn-off of inductive loads by the high-side switch, the kickback voltage generated by the inductance is clamped by the internal clamp to a voltage of -56v (typ) relative to v dd . large inductance and higher initial currents in the inductive load increase the time to until the inductance is demag - netized. large energy dissipated in the chip through the voltage clamp. the MAX14912/max14913 feature safe demagnetization, which allows inductive loads of any value to be turned off. in high-side mode, the MAX14912/ max14913 do not have a limitation to the maximum inductive load that can be switched by the outs. board layout high-speed switches require proper layout and design procedures for optimal performance. ensure that power- supply bypass capacitors are placed as close as possible to the device. connect all v dd pins to a v dd plane. ensure that all pins have no more than 10m between them. in this case, a 1f capacitor should be placed as close as possible to the v dd pins. in case low-resistance paths are not possible between the v dd pins, bypass each pin to gnd through a 100nf capacitor. surge protection the max14913 out_ pins achieve 1kv/(42 + 0.5f) iec-61000-4-5 1.2s/50s surge ratings by using only a tvs protection diode on v dd , as shown in the typical application circuit . a suppressor/tvs diode should be used between v dd and gnd to clamp high-surge transients on the v dd supply input and surges from the o_ outputs. the standoff voltage should be higher than the rated operating voltage of the equipment, while the breakdown voltage should be below 75v. reverse currents into out if currents flow into the out_ pins, the device will heat up due to internal currents that flow through the device to pgnd. the allowed reverse currents thus depend on v dd , the ambient temperature and the thermal resistance. at 25c ambient temperature the reverse current into one out should be limited to 1a at v dd = 36v and 2a at v dd = 24v. driving higher currents into out can destroy the device thermally. enable time at power-up and/or when en is pulled high, all in_ signals must be kept low for at least 20ms. maxim integrated 28 MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
+ denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. *future productcontact factory for availability. package type package code outline no. land pattern no. 56 qfn-ep k5688+1 21-100026 90-100006 part temp range package package code package body size lead pitch MAX14912akn+* -40c to +125c qfn56 k5688+1 8mm x 8mm 0.5mm MAX14912akn+t* -40c to +125c qfn56 k5688+1 8mm x 8mm 0.5mm max14913akn+ -40c to +125c qfn56 k5688+1 8mm x 8mm 0.5mm max14913akn+t -40c to +125c qfn56 k5688+1 8mm x 8mm 0.5mm maxim integrated 29 chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. ordering information MAX14912/max14913 octal high-speed, high-side switch/push-pull driver www.maximintegrated.com
revision number revision date description pages changed 0 12/15 initial release 1 5/16 updated electrical characteristics table 1, 3C5, 7, 9, 23, 29 2 6/16 updated v pmp abs max limit 3 3 8/16 updated text and diagrams 2, 3, 9C11, 14, 18, 19, 24C26, 28 ? 2016 maxim integrated products, inc. 30 revision history maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifcations without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. MAX14912/max14913 octal high-speed, high-side switch/push-pull driver for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.

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